Clock gating for low power circuit design by Merge and split methods
نویسنده
چکیده
In present VLSI technology energy dissipation is an important factor to be considered among other factors like area, speed and performance in portable devices. The size reduction and complexity of portable devices have resulted in large amount of power dissipation in the devices. As a result low power designs have become inevitable part of today’s devices. In this paper low power dissipation is achieved by using clock gating technique. It reduces the dynamic power dissipation by controlling the clock whenever it is not in use. Merge and Split clock gated concepts were applied in our design to find the low power dissipation. Experimental results show that our design achieves low power dissipation.
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